[Mpi3-rma] MPI-3 UNIFIED model clarification

[Jed Brown]

"Sur, Sayantan" <sayantan.sur at intel.com> writes:
> What this discussion brings to light is a lack of common understanding of the following comment on Pg 436, line 37-39:
>
> " In the RMA unified model, public and private copies are identical and updates via put
> or accumulate calls are eventually observed by load operations without additional RMA
> calls."
>
> I take "eventually" to mean locks/flushes. But it seems that not everyone shares that interpretation? 

I think something along the lines of the subsequent advice section
should have been in the main paragraph.

    Advice to users. If accesses in the RMA unified model are not
    synchronized (with locks or flushes, see Section 11.5.3), load and
    store operations might observe changes to the memory while they are
    in progress. The order in which data is written is not specified
    unless further synchronization is used. This might lead to
    inconsistent views on memory and programs that assume that a
    transfer is complete by only checking parts of the message are
    erroneous. (End of advice to users.)


Specifically, architecture-specific coaxing (memory fences) might be
required to see the result (ever; no guarantee that it happens
"eventually" on its own), especially if one would like to preserve some
ordering.
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