[Mpi3-rma] Memory barriers in MPI_WIN_LOCK_ALL mode
htor at illinois.edu
Tue Oct 30 09:30:03 CDT 2012
On Tue, Oct 30, 2012 at 08:00:12AM -0700, Jed Brown wrote:
> On Tue, Oct 30, 2012 at 6:54 AM, Torsten Hoefler <htor at illinois.edu>
> >>> I don't think the target process can guarantee that the PUT is
> >>> visible to a load/store without an additional memory barrier.
> >> The flush of the source process has to ensure that.
> > How?
> See above, mfence.
> Even in shared memory, the mfence is useless for guaranteeing visibility
> to any other thread/process. For visibility on architectures that reorder
> loads, the P1 must issue a read memory barrier after seeing the hand wave
> and before reading from the window.
My stated assumption was TSO/x86, which does not reorder loads. You are
of course correct in the general case (ARM for example).
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