[Mpi3-rma] Memory barriers in MPI_WIN_LOCK_ALL mode

Jed Brown jedbrown at mcs.anl.gov
Tue Oct 30 10:00:12 CDT 2012

On Tue, Oct 30, 2012 at 6:54 AM, Torsten Hoefler <htor at illinois.edu> wrote:

> >>> I don't think  the target process can guarantee that the PUT is
> >>> visible to a load/store  without an additional memory barrier.
> >> The flush of the source process has to ensure that.
> >
> > How?
> See above, mfence.

Even in shared memory, the mfence is useless for guaranteeing visibility to
any other thread/process. For visibility on architectures that reorder
loads, the P1 must issue a read memory barrier after seeing the hand wave
and before reading from the window.
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