[Mpi3-rma] MPI RMW operations
Shipman, Galen M.
gshipman at ornl.gov
Thu Mar 27 17:50:29 CDT 2008
Rajeev,
On Mar 27, 2008, at 6:05 PM, Rajeev Thakur wrote:
> Some comments:
>
> * Are the semantics supposed to be that the original value at the
> target is
> read and stored at the result_addr on the origin (like a Get), and the
> target memory is updated with the result of the reduction operation
> (like
> Accumulate)?
Exactly, the value prior to the update is "returned" in the
result_addr and the target memory is updated with the result of the
operation.
>
> * What are the semantics of the two-operand versions?
>
For MPI_RMW2_COMP_SWAP:
operand_addr is the comparand, operand2_addr is the operand.
Comparand is compared to the value at the target, if these values are
equal then operand is written to the value at the target.
For MPI_RMW2_MASK_SWAP:
operand_addr is the maskarand, operand2_addr is the operand.
Maskarand identifies the bits within the value at the target to be
updated with the corresponding bits from operand.
> * Why is there no count, datatype at the target like in Accumulate?
This is intentional, datatypes and count must match on passive and
active sides and are therefore implicit.
>
> * When assert == MPI_MODE_PASSIVE_EPOCH_IMPLICIT, what is the lock
> type for
> the Win_lock -- shared or exclusive?
As all MPI_RMW/2 operations have the potential of updating the remote
value and may therefore cause conflicts I would expect this to be an
MPI_LOCK_EXCLUSIVE
> Also, Win_unlock takes only two
> parameters.
>
Yes, the example needs to be corrected.
Thanks for the comments,
Galen
> * Regarding the interaction with explicit epochs of Rmw when assert ==
> MPI_MODE_PASSIVE_EPOCH_IMPLICIT, it should be the same as the
> interaction of
> its equivalent sequence, namely, Lock - Rmw - Unlock. In other
> words, there
> shouldn't be another epoch around it on the same process (nested
> epochs not
> allowed), and the epochs on other processes must not conflict.
>
> Rajeev
>
>
>> -----Original Message-----
>> From: mpi3-rma-bounces at lists.mpi-forum.org
>> [mailto:mpi3-rma-bounces at lists.mpi-forum.org] On Behalf Of
>> Shipman, Galen M.
>> Sent: Monday, March 24, 2008 10:10 PM
>> To: mpi3-rma at lists.mpi-forum.org
>> Subject: [Mpi3-rma] MPI RMW operations
>>
>>
>> Howard and I have been working on the RMW operations listed
>> below for
>> consideration.
>>
>> - Galen Shipman - ORNL
>>
>>
>> Single operand RMW operations
>>
>> MPI_Rmw(void *operand_addr,
>> int count,
>> MPI_Datatype datatype,
>> void *result_addr,
>> int target_rank,
>> MPI_Aint target_disp,
>> int assert,
>> MPI_RMW_Op op,
>> MPI_Win win)
>>
>>
>> Two operand RMW operations
>>
>> MPI_Rmw2(void *operand_addr,
>> int count,
>> MPI_Datatype datatype,
>> void *operand2_addr,
>> void *result_addr,
>> int target_rank,
>> MPI_Aint target_disp,
>> int assert,
>> MPI_RMW_2_Op op,
>> MPI_Win win)
>>
>>
>>
>> MPI_RMW_Op Predefined RMW single operand operations
>> The following predefined operations are supplied for MPI_RMW
>> and related
>> functions. These operations are invoked by placing the
>> following in op.
>>
>> Name Meaning
>>
>> MPI_RMW_INC increment
>> MPI_RMW_PROD product
>> MPI_RMW_SUM sum
>> MPI_RMW_LAND logical and
>> MPI_RMW_LOR logical or
>> MPI_RMW_LXOR logical xor
>> MPI_RMW_BAND binary and
>> MPI_RMW_BOR binary or
>> MPI_RMW_BXOR binary xor
>> MPI_RMW_SWAP swap value
>>
>> MPI_RMW_2_Op Predefined RMW two operand operations
>>
>> Name Meaning
>>
>> MPI_RMW2_MASK_SWAP swap masked bits
>> MPI_RMW2_COMP_SWAP compare and swap
>>
>> Note: MPI_RMW2_COMP_SWAP is an equality comparison, we may wish to
>> consider multiple comparison operations such as >, >=, <, <=, ==, <>.
>>
>> Both MPI_Rmw and MPI_Rmw2 take an assert argument.
>> When assert == MPI_MODE_PASSIVE_EPOCH_IMPLICIT MPI_Rmw/2 is
>> equivalent to:
>>
>> MPI_Win_lock(target_rank,0,win);
>> MPI_Rmw(.....);
>> MPI_Win_unlock(target_rank,0,win);
>>
>> When assert == MPI_MODE_PASSIVE_EPOCH_IMPLICIT | MPI_MODE_NOCHECK
>> the MPI library knows that the window lock at the target need not be
>> acquired.
>>
>>
>>
>>
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>>
>>
>
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