[Mpi3-rma] MPI-3 UNIFIED model clarification

Underwood, Keith D keith.d.underwood at intel.com
Mon Jul 29 22:48:29 CDT 2013

> On 07/29/2013 10:18 PM, Underwood, Keith D wrote:
> >And, um, technically, if loads can be hoisted  across the MPI_Recv,
> >then the MPI_Recv semantics are incorrect and  you have to have a
> >memory barrier in MPI_Recv.
> Why is reordering not permitted for two unrelated memory loads?  AFAIK,
> ARM allows that.

I'm talking about a load of the data written for the MPI_Recv getting hoisted across MPI_Recv.  There is no guarantee of anything in that MPI_Recv actually touching the data being received.  There is no guarantee of anything telling the microarchitecture that you are doing an illegal hoist across that receive.


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