[Mpi3-rma] [EXTERNAL] Re: Memory barriers in MPI_WIN_LOCK_ALL mode
jhammond at alcf.anl.gov
Tue Oct 30 10:13:56 CDT 2012
>>Even in shared memory, the mfence is useless for guaranteeing visibility
>>to any other thread/process. For visibility on architectures that reorder
>>loads, the P1 must issue a read memory barrier after seeing the hand wave
>>and before reading from the window.
> Right, so it's possible that on platforms that require a read barrier
> because they reorder loads, the MPI implementation will not be able to
> support the unified model. Or they'll have to have a read barrier before
> every get in the unified model or some such thing.
Seems perfectly reasonable to have a read barrier before a Get on a
processor with a weaker memory model.
Argonne Leadership Computing Facility
University of Chicago Computation Institute
jhammond at alcf.anl.gov / (630) 252-5381
More information about the mpiwg-rma